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C8051F380/1/2/3/4/5/6/7/C
17.1. Power-On Reset
During power-up, the device is held in a reset state and the RST pin is driven low until V DD settles above
V RST . A delay occurs before the device is released from reset; the delay decreases as the V DD ramp time
increases (V DD ramp time is defined as how fast V DD ramps from 0 V to V RST ). Figure 17.2. plots the
power-on and V DD monitor event timing. The maximum V DD ramp time is 1 ms; slower ramp times may
cause the device to be released from reset before V DD reaches the V RST level. For ramp times less than
1 ms, the power-on reset delay (T PORDelay ) is typically less than 0.3 ms.
On exit from a power-on or V DD monitor reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1.
When PORSF is set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is
cleared by all other resets). Since all resets cause program execution to begin at the same location
(0x0000) software can read the PORSF flag to determine if a power-up was the cause of reset. The con-
tent of internal data memory should be assumed to be undefined after a power-on reset. The V DD monitor
is enabled following a power-on reset.
VDD
V RST
t
Logic HIGH
Logic LOW
RST
T PORDelay
VDD
Power-On
Reset
Monitor
Reset
Figure 17.2. Power-On and V DD Monitor Reset Timing
130
Rev. 1.4
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